(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of improved buried contact resistance in the fabrication of integrated circuits.
(2) Description of the Prior Art
Referring to FIG. 1, a typical buried contact is formed by depositing a doped layer of polysilicon 14 over and on the planned buried contact regions in a semiconductor substrate 10 and heating the structure. The buried contact regions 16 are doped by outdiffusion of dopants from the doped polysilicon layer into the silicon substrate. The doped polysilicon layer 14 is allowed to remain on the buried contact regions as their contacts. Gate electrodes 18 and source and drain regions 20 are formed in and on the semiconductor substrate. One of the source/drain regions 20 contacts the buried contact region 16. The desired current path is illustrated by dotted line 30 in FIG. 1. The path goes from the polysilicon 14 directly through the buried N+ region 16 to the N+ source or drain region 20.
If there is misalignment of the mask during etching of the polysilicon 18, the resistance of the buried contact will be increased. If the mask is shifted to the left, as shown in FIG. 2, a portion of the semiconductor substrate within the buried contact area will be exposed. During polysilicon overetching, a buried contact trench 22 will be etched. The current path in FIG. 2 is illustrated by dotted line 32. In this case, the path goes from the polysilicon 14 through the buried contact 16, then around the trench 22 and finally to the source/drain region 20. The area around the trench 22 is N- because the N- dopant, for an NLDD MOSFET structure, is implanted before the sidewall formation. Since N- is resistive rather than conductive, resistance is increased, leading to decreased device performance. If the mask is shifted to the right, as shown in FIG. 3, the N+ source/drain regions 20 will not contact the buried N+ region 16 directly, but an N- region 24 will come between the two N+ regions. The current path in FIG. 3 is illustrated by dotted line 34. In this case, the path goes from the polysilicon 14 through the buried contact 16, through the N- region 24, and finally to the source/drain region 20. As in the case above, the N- region adds resistance, decreasing device performance.
U.S. Pat. No. 5,350,712 to Shibata teaches the use of an additional metal width around a metal line to overcome mask misalignment problems causing etching of the semiconductor substrate. Co-pending U.S. patent application Ser. No. 08/405719, now U.S. Pat. No. 5,494,848 to H. W. Chin filed on Mar. 17, 1994 teaches a method using an inverse tone of the buried contact mask to make a photoresist mask covering the buried junction area and adding an additional bias-on either side of the mask to protect the buried junction area during over-etch so that a misalignment of the mask will not cause the formation of a buried contact trench. Co-pending U.S. Pat. application Ser. No. 08/488,764, now U.S. Pat. No. 5,525,552 to J. M. Huang uses a high dielectric constant spacer material for the LDD spacer to provide better immunity of the buried contact trench.